US 12,243,459 B2
Flip-flop circuit, driver circuit, display panel, display device, input/output device, and data processing device
Kouhei Toyotaka, Atsugi (JP); Kazunori Watanabe, Machida (JP); Susumu Kawashima, Atsugi (JP); Daisuke Kubota, Atsugi (JP); Tetsuji Ishitani, Atsugi (JP); and Akio Yamashita, Atsugi (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Jan. 12, 2023, as Appl. No. 18/096,117.
Application 18/096,117 is a continuation of application No. 17/269,736, granted, now 11,562,675, previously published as PCT/IB2019/057561, filed on Sep. 9, 2019.
Claims priority of application No. 2018-177156 (JP), filed on Sep. 21, 2018.
Prior Publication US 2023/0154369 A1, May 18, 2023
Int. Cl. G09G 3/20 (2006.01); G06F 3/041 (2006.01)
CPC G09G 3/20 (2013.01) [G06F 3/041 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/08 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2320/0247 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first circuit comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and a first output terminal,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor and a second output terminal,
wherein one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor and a third output terminal,
wherein a first gate of the first transistor is electrically connected to a first gate of the third transistor and a first gate of the fifth transistor,
wherein a first gate of the fourth transistor is electrically connected to the first gate of the second transistor and the first gate of the sixth transistor through the seventh transistor, and
wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring configured to supply a clock signal.