| CPC G09F 9/30 (2013.01) [H10K 50/00 (2023.02); H01L 29/7869 (2013.01); H10K 59/00 (2023.02)] | 13 Claims | 

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               1. A semiconductor device comprising: 
            a substrate; 
                a first insulating layer over the substrate; 
                a semiconductor layer, comprising indium, gallium, and zinc, over the first insulating layer; 
                a second insulating layer, comprising a metal element, over the semiconductor layer; 
                a third insulating layer over the second insulating layer; 
                a fourth insulating layer over the third insulating layer; 
                a first conductive layer over the fourth insulating layer; 
                a fifth insulating layer over the first conductive layer; and 
                a second conductive layer and a third conductive layer over the fifth insulating layer, 
                wherein the semiconductor layer comprises a channel formation region of a transistor, 
                wherein the first conductive layer functions as a gate electrode of the transistor, 
                wherein the first conductive layer is provided in a first opening which is provided in the second insulating layer and the third insulating layer, 
                wherein the second conductive layer and the third conductive layer are electrically connected to the semiconductor layer, 
                wherein the second conductive layer is provided in a second opening which is provided in the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer, and 
                wherein the third conductive layer is provided in a third opening which is provided in the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer. 
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