US 12,243,125 B2
Controlling coarse pixel size from a stencil buffer
Karthik Vaidyanathan, Berkeley, CA (US); Prasoonkumar Surti, Folsom, CA (US); Hugues Labbe, Folsom, CA (US); Atsuo Kuwahara, Portland, OR (US); Sameer KP, Bangalore (IN); Jonathan Kennedy, Bristol (GB); Murali Ramadoss, Folsom, CA (US); Michael Apodaca, Folsom, CA (US); and Abhishek Venkatesh, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 22, 2023, as Appl. No. 18/517,318.
Application 18/517,318 is a continuation of application No. 17/666,193, filed on Feb. 7, 2022, granted, now 11,869,119.
Application 17/666,193 is a continuation of application No. 16/919,839, filed on Jul. 2, 2020, granted, now 11,244,479, issued on Feb. 8, 2022.
Application 16/919,839 is a continuation of application No. 16/142,866, filed on Sep. 26, 2018, granted, now 10,706,591, issued on Jul. 7, 2020.
Application 16/142,866 is a continuation of application No. 15/483,701, filed on Apr. 10, 2017, granted, now 10,109,078, issued on Oct. 23, 2018.
Prior Publication US 2024/0161356 A1, May 16, 2024
Int. Cl. G06T 1/60 (2006.01); G06T 1/20 (2006.01); G06T 11/00 (2006.01); G06T 15/00 (2011.01)
CPC G06T 11/001 (2013.01) [G06T 1/20 (2013.01); G06T 1/60 (2013.01); G06T 15/005 (2013.01); G06T 2210/52 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a two-dimensional (2D) texture memory; and
logic to:
identify a stencil value that is associated with the 2D texture memory, and
determine a number of pixels that are to share an invocation of a pixel shader based on the stencil value, wherein the number of pixels is to be controlled via a stencil buffer.