| CPC G06T 1/20 (2013.01) [G06T 1/60 (2013.01); G06T 2200/28 (2013.01)] | 20 Claims |
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1. A graphics processor, comprising:
geometry processing logic arranged, for each of a sequence of tasks, to perform geometry processing and write a data structure resulting therefrom to a memory, the data structure for each task comprising respective tile data for each of a plurality of tiles of a render area;
fragment processing logic arranged to read the tile data of each of the tasks from the memory and perform fragment processing based thereon; and
a memory management circuit arranged to allocate memory regions from the memory to be used by the geometry processing logic to write the tile data, and to deallocate each of the memory regions after the tile data therein has been processed by the fragment processing logic; wherein:
for each task, the memory management circuit is configured to track which of the memory regions are allocated to hold the tile data of which of a plurality of spatial units into which the render area is divided, each spatial unit encompassing one or more tiles;
for each respective one of the spatial units, the fragment processing logic is configured so as, once it has finished processing the tile data of the respective spatial unit, to send an identifier of the respective spatial unit to the memory management circuit;
the memory management circuit is configured to deallocate each respective one of the memory regions once the memory management circuit has received the identifier of every spatial unit to which that region is allocated; and
the graphics processor further comprises a blocking circuit enabling the fragment processing logic to start processing the tile data of a second of said sequence of tasks while the memory management circuit is still deallocating some of the memory regions allocated to the spatial units of a first of said sequence of tasks, the blocking circuit being configured to prevent the identifiers of the spatial units of the second task being passed to the memory management circuit until the memory management circuit indicates that it has completed deallocating the memory regions allocated to all the spatial units in the first task.
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