US 12,242,949 B2
Compute-in-memory devices, systems and methods of operation thereof
Prashant Kumar Saxena, Fremont, CA (US); Vineet Agrawal, San Jose, CA (US); and Venkatraman Prabhakar, Pleasanton, CA (US)
Assigned to Infineon Technologies LLC, San Jose, CA (US)
Filed by Infineon Technologies LLC, San Jose, CA (US)
Filed on Mar. 29, 2021, as Appl. No. 17/215,372.
Prior Publication US 2022/0309328 A1, Sep. 29, 2022
Int. Cl. G06N 3/08 (2023.01); G06F 7/544 (2006.01); G06N 3/063 (2023.01); G11C 16/04 (2006.01); G11C 16/24 (2006.01); H03M 1/12 (2006.01)
CPC G06N 3/063 (2013.01) [G06F 7/5443 (2013.01); G06N 3/08 (2013.01); G11C 16/0466 (2013.01); G11C 16/24 (2013.01); H03M 1/12 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method, comprising:
storing weight values in storage elements of nonvolatile memory (NVM) cells of a NVM cell array, the NVM cell array having rows and columns, wherein one row and one column of the NVM cells are coupled to a word line and a bit line respectively;
for at least one row, generating a multiply-accumulate (MAC) result for the row by applying input values on bit lines, each MAC result comprising a summation of an analog current or voltage that is a function of each input value and a corresponding weight value stored by the NVM cells of the row; and
by operation of at least one multiplexer, connecting one of a plurality of the rows to an analog-to-digital converter (ADC) circuit to convert the analog current or voltage of the row into a digital MAC value; wherein the storage element of each NVM cell is configured to store a weight value that can vary between no less than three different values.