US 12,242,906 B1
Hardware-implemented hybrid analog-digital mixed-mode matrix multiply-add processing element for machine learning applications
Georgios Konstadinidis, San Jose, CA (US)
Filed by Georgios Konstadinidis, San Jose, CA (US)
Filed on Oct. 25, 2024, as Appl. No. 18/927,565.
Int. Cl. G06F 1/00 (2006.01); G06J 1/00 (2006.01); H03M 1/12 (2006.01)
CPC G06J 1/00 (2013.01) [H03M 1/1245 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A hardware-implemented hybrid analog-digital mixed-mode matrix multiply-add processing element (PE) for machine learning (ML) applications comprising:
a 4 bit multiply processing element (PE) that performs a multiplication function;
a first circuit that implements the 4 bit multiply PE to calculate a first current result based on a first reference current;
a second circuit that implements the 4 bit multiply PE to calculate a second current result based on a second reference current; and
a connection between a first output of the first circuit and a second output of the second circuit to produce a combined current resulting from implementation of a multiply-add function that calculates a sum of the first current result and the second current result.