US 12,242,894 B2
Technique for hardware activation function computation in RNS artificial neural networks
Athanasios Stouraitis, Abu Dhabi (AE); Sakellariou Vasileios, Abu Dhabi (AE); Vasileios Paliouras, Patras (GR); Ioannis Kouretas, Patras (GR); and Hani Saleh, Abu Dhabi (AE)
Assigned to Khalifa University of Science and Technology, Abu Dhabi (AE)
Filed by Khalifa University of Science and Technology, Abu Dhabi (AE)
Filed on Mar. 31, 2023, as Appl. No. 18/193,635.
Claims priority of application No. 20220100431 (GR), filed on May 24, 2022.
Prior Publication US 2023/0385115 A1, Nov. 30, 2023
Int. Cl. G06F 9/50 (2006.01); G06F 7/72 (2006.01)
CPC G06F 9/5027 (2013.01) [G06F 7/72 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A device comprising:
a processor;
a non-transitory computer-readable memory comprising instructions executable by the processor to cause the processor to perform one or more operations associated with at least one of an input to or an output from a neural network; and
a neural network accelerator configured to implement, in hardware, at least a part of the neural network by using a residue number system (RNS), wherein:
at least one function of the neural network has a corresponding approximation in the RNS,
the at least one function is provided by implementing the corresponding approximation in hardware, and
the operations include:
receiving the input,
performing a base extension on the input,
generating a mapped value based on the base extension, and
determining an index by at least using the mapped value and a lookup table operation.