| CPC G06F 9/3888 (2023.08) [G06F 8/41 (2013.01); G06F 8/76 (2013.01)] | 27 Claims |

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1. A system to support multiple instruction set generation from a single specification of an integrated circuit (IC), comprising:
a specification compiler configured to
accept as input a first instruction set of a plurality of first instructions in a specification format, wherein the first instruction set defines a design pattern of one or more specifications of the IC and is independent of any implementation or platform of the IC;
convert the first instruction set into a second instruction set comprising a plurality of second instructions in an intermediate format, wherein the second instruction set in the intermediate format represents the same design pattern of the IC as the first instruction set; and
a language compiler configured to accept and compile the second instruction set into a plurality of third instruction sets using a template specific to a language to compile for a specific implantation or platform of the IC, wherein each instruction set of the plurality of third instruction sets comprises a plurality of third instructions in the specific language, and wherein the template specific to the language maps context of one or more fields in the intermediate format to the specific language.
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