US 12,242,855 B2
Coprocessor operation bundling
Aditya Kesiraju, Los Gatos, CA (US); Brett S. Feero, Austin, TX (US); Nikhil Gupta, Santa Clara, CA (US); and Viney Gautam, San Jose, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jul. 28, 2023, as Appl. No. 18/361,212.
Application 18/361,212 is a continuation of application No. 17/527,872, filed on Nov. 16, 2021, granted, now 11,755,328.
Application 17/527,872 is a continuation of application No. 16/242,151, filed on Jan. 8, 2019, granted, now 11,210,100, issued on Dec. 28, 2021.
Prior Publication US 2024/0036870 A1, Feb. 1, 2024
Int. Cl. G06F 9/38 (2018.01); G06F 9/30 (2018.01); G06F 9/48 (2006.01); G06F 9/52 (2006.01)
CPC G06F 9/3814 (2013.01) [G06F 9/30018 (2013.01); G06F 9/30038 (2023.08); G06F 9/30043 (2013.01); G06F 9/3816 (2013.01); G06F 9/3877 (2013.01); G06F 9/4881 (2013.01); G06F 9/522 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a processor that is configured to receive instructions to be executed by the processor and coprocessor instructions to be executed by a coprocessor, wherein the processor includes:
a coprocessor issue circuit configured to issue the coprocessor instructions to an interface circuit; and
the interface circuit, wherein the interface circuit includes a buffer having a plurality of buffer entries, and wherein the buffer is configured to accumulate, in a buffer entry of the plurality of buffer entries, data describing multiple ones of the coprocessor instructions, the data including respective source data specified by one or more of the first multiple coprocessor instructions;
wherein the interface circuit is further configured to write a command to the buffer entry, the command comprising opcodes corresponding to respective ones of the multiple coprocessor instructions, close the buffer entry, and transmit the data accumulated in the buffer entry to the coprocessor; and
the coprocessor, wherein the coprocessor is configured to execute the multiple coprocessor instructions described by the data, wherein the coprocessor is configured to execute the coprocessor instructions at up to a first rate, and wherein the interface circuit is configured to provide coprocessor instruction at an average rate that matches the first rate.