| CPC G06F 9/30047 (2013.01) | 20 Claims |
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1. A computing system comprising:
a primary processor configured to execute at least a plurality of executable instructions and to generate first instruction data associated with plurality of executable instructions;
a secondary processor configured to execute at least the plurality of executable instructions one or more clock cycles behind the primary processor and to generate secondary instruction data associated with the plurality of executable instructions;
a first first-in first-out (FIFO) buffer associated with the primary processor;
a second FIFO buffer associated with the secondary processor;
circuitry configured for storing some of the first instruction data in the first FIFO buffer for storing at least some of the second instruction data in the first FIFO buffer;
compare circuitry configured for comparing at least a first portion of the first instruction data that is associated with a given clock cycle with at least a second portion of the second instruction data associated with the given clock cycle; and
control circuitry configured for causing the primary processor and the second processor to at least temporarily halt execution of the plurality of executable instructions responsive to the compare circuitry determining a mismatch between the first portion and the second portion.
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