US 12,242,828 B2
Software compilation for networked processing system
Norman Vernon Douglas Stewart, Markham (CA); Mihir Shaileshbhai Doctor, Santa Clara, CA (US); and Mingliang Lin, Shanghai (CN)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US); and ATI Technologies ULC, Markham (CA)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US); and ATI Technologies ULC, Markham (CA)
Filed on Nov. 1, 2022, as Appl. No. 17/978,902.
Prior Publication US 2024/0143295 A1, May 2, 2024
Int. Cl. G06F 9/46 (2006.01); G06F 8/41 (2018.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01); G06F 9/455 (2018.01); G06F 11/14 (2006.01)
CPC G06F 8/41 (2013.01) [G06F 9/5033 (2013.01); G06F 9/30036 (2013.01); G06F 9/30065 (2013.01); G06F 9/30101 (2013.01); G06F 9/3887 (2013.01); G06F 9/45558 (2013.01); G06F 11/1428 (2013.01); G06F 11/1456 (2013.01); G06F 11/1469 (2013.01); G06F 11/1492 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for compiling, the method comprising:
in response to a first instruction not including an explicit indication that a first auxiliary processor is to execute the first instruction and targeting a first resource determined based on a system topology at compile-time to be associated with the first auxiliary processor, including the first instruction in a first executable for the first auxiliary processor; and
in response to a second instruction including an explicit indication that the first auxiliary processor is to execute the second instruction and targeting a second resource determined based on the system topology at compile-time to be associated with a second auxiliary processor, including the second instruction in the first executable for the first auxiliary processor.