US 12,242,783 B1
Data-driven clock port and clock signal recognition
Gung-Yu Pan, Baoshan Township (TW); Ssu-Hsien Li, Hsinchu (TW); Che-Hua Shih, Hsinchu (TW); Yi-An Chen, Hsinchu (TW); and Chia-Chih Yen, Taipei (TW)
Assigned to Synopsys, Inc., Mountain View, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Feb. 28, 2022, as Appl. No. 17/683,216.
Claims priority of provisional application 63/154,420, filed on Feb. 26, 2021.
Int. Cl. G06F 30/3308 (2020.01); G06F 30/20 (2020.01); G06F 30/27 (2020.01); G06F 30/367 (2020.01); G06F 30/396 (2020.01); G06F 30/398 (2020.01)
CPC G06F 30/3308 (2020.01) [G06F 30/20 (2020.01); G06F 30/27 (2020.01); G06F 30/367 (2020.01); G06F 30/396 (2020.01); G06F 30/398 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
generating a plurality of output values at an output port of a circuit simulation component by applying, during a simulation, a plurality of input values to a first input port of the circuit simulation component;
calculating a correlation vector based on bit sequences in the plurality of input values and bit sequences in the plurality of output values; and
determining, by a processor, the first input port is a clock port by applying a machine learning model to the correlation vector.