US 12,242,760 B2
Storage traffic pattern detection in memory devices
Luca Porzio, Casalnuovo di Napoli (IT); Roberto Izzi, Caserta (IT); Nicola Colella, Capodrise (IT); Danilo Caraccio, Milan (IT); and Alessandro Orlando, Milan (IT)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Aug. 25, 2023, as Appl. No. 18/456,016.
Application 18/456,016 is a continuation of application No. 17/856,556, filed on Jul. 1, 2022, granted, now 11,740,837.
Application 17/856,556 is a continuation of application No. 16/937,213, filed on Jul. 23, 2020, granted, now 11,379,153, issued on Jul. 5, 2022.
Prior Publication US 2023/0409242 A1, Dec. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 12/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01); G06F 12/0646 (2013.01); G06F 2212/657 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device;
a controller coupled to the memory device and configured to:
receive a plurality of commands;
identify a received command of the plurality of commands whose corresponding data is written directly to the memory device bypassing a cache;
determine a metadata area of the memory device based on the identifying of the received command whose corresponding data is written to the memory device bypassing the cache; and
responsive to determining that a start logical block address (LBA) and an end LBA for a different write command is contiguous with a start LBA and an end LBA of the metadata area, update the start LBA and the end LBA of the metadata area to include the start LBA and the end LBA of the different write command.