US 12,242,759 B2
Quasi-volatile memory device with a back-channel usage
Robert D. Norman, Pendleton, OR (US); and Eli Harari, Saratoga, CA (US)
Assigned to SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed by SunRise Memory Corporation, San Jose, CA (US)
Filed on Feb. 5, 2024, as Appl. No. 18/432,930.
Application 18/432,930 is a continuation of application No. 17/688,095, filed on Mar. 7, 2022, granted, now 11,954,363.
Application 17/688,095 is a continuation of application No. 16/843,769, filed on Apr. 8, 2020, granted, now 11,301,172, issued on Apr. 12, 2022.
Claims priority of provisional application 62/867,604, filed on Jun. 27, 2019.
Claims priority of provisional application 62/831,611, filed on Apr. 9, 2019.
Prior Publication US 2024/0176546 A1, May 30, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 11/10 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); G06F 16/188 (2019.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G06F 11/1068 (2013.01); G06F 13/4027 (2013.01); G06F 13/4282 (2013.01); G06F 16/188 (2019.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); G06F 2213/0026 (2013.01); H01L 2225/06541 (2013.01)] 40 Claims
OG exemplary drawing
 
1. A memory module, comprising:
an internal bus;
a first memory-mapped device coupled to the internal bus, the first memory-mapped device comprising a controller and a plurality of memory circuits, the controller and the memory circuits each being provided on a semiconductor die, each semiconductor die being bonded to another one of the semiconductor dies, wherein each memory circuit comprises (i) one or more three-dimensional memory arrays; and (ii) a plurality of interconnect conductors which communicate data and control signals between the controller and the memory circuit, such data and control signals being associated operations of the memory circuit; and
a second memory-mapped device coupled to the internal bus bus, wherein the internal bus communicates data and control signals between the controller and the second memory-mapped device, such data and control signals being associated with the operations of the second memory-mapped device.