US 12,242,755 B2
Adaptive enhanced corrective read based on write and read temperature
Zhenming Zhou, San Jose, CA (US); Murong Lang, San Jose, CA (US); Ching-Huang Lu, Fremont, CA (US); and Nagendra Prasad Ganesh Rao, Folsom, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Feb. 6, 2024, as Appl. No. 18/434,616.
Application 18/434,616 is a continuation of application No. 17/830,625, filed on Jun. 2, 2022, granted, now 11,947,831.
Prior Publication US 2024/0241664 A1, Jul. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0652 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
receiving a request to perform a read operation on a segment of the memory device;
determining whether a temperature offset value of the segment satisfies a threshold criterion determined based on a program erase cycle count of the segment; and
responsive to determining that the temperature offset value satisfies the threshold criterion, performing a corrective read operation on the segment of the memory device, wherein a sense time parameter of the corrective read operation is modified according to the temperature offset value and the program erase cycle count.