US 12,242,740 B2
Data storage device and method for hiding tweak generation latency
Mark Branstad, Rochester, MN (US); Martin Lueker-Boden, Fremont, CA (US); and Lunkai Zhang, Portland, OR (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Jul. 19, 2023, as Appl. No. 18/223,662.
Claims priority of provisional application 63/461,953, filed on Apr. 26, 2023.
Prior Publication US 2024/0361925 A1, Oct. 31, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0623 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 18 Claims
OG exemplary drawing
 
1. In a data storage device comprising a memory and an AES-XTS decryption engine, a method comprising:
receiving a read request comprising a read address;
reading encrypted data from the memory, wherein the encrypted data is read from a location in the memory associated with the read address;
while the encrypted data is being read from the memory:
generating a tweak value from the read address during latency associated with reading encrypted data from the memory; and
storing the tweak value in a buffer in the data storage device;
receiving the encrypted data read from the memory, wherein the encrypted data is received out-of-order with respect to read requests processed by the memory; and
after receiving the encrypted data from the memory:
identifying a location of the tweak value in the buffer using a current cycle pointer; and
sending the tweak value and the encrypted data to the AES-XTS decryption engine, wherein the encrypted data is decryptable by the AES-XTS decryption engine without the AES-XTS decryption engine having to wait for the tweak value to be generated.