US 12,242,732 B2
Semiconductor apparatus with program operation control
Hyung Jin Choi, Icheon-si (KR); Gwi Han Ko, Icheon-si (KR); and Chan Hui Jeong, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Nov. 8, 2022, as Appl. No. 17/983,115.
Claims priority of application No. 10-2022-0069413 (KR), filed on Jun. 8, 2022.
Prior Publication US 2023/0400986 A1, Dec. 14, 2023
Int. Cl. G11C 16/10 (2006.01); G06F 3/06 (2006.01); G11C 5/14 (2006.01); G11C 11/409 (2006.01); G11C 16/34 (2006.01)
CPC G06F 3/0616 (2013.01) [G06F 3/0629 (2013.01); G06F 3/0679 (2013.01); G11C 5/141 (2013.01); G11C 11/409 (2013.01); G11C 16/3436 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor apparatus comprising:
a memory cell array; and
control circuit configured to perform a program operation on target cells within the memory cell array, the program operation comprises a plurality of loops,
wherein the control circuit is configured to perform, during the program operation, at least one of a first program control operation and a second program control operation,
wherein the control circuit is configured to perform the first program control operation by applying a bit line voltage having a first predetermined level to bit lines in loops in which a pass voltage having a first level is applied among the plurality of loops, and by applying the bit line voltage having a higher level than the first predetermined level to the bit lines in loops in which the pass voltage having a second level higher than the first level is applied among the plurality of loops, and
wherein the control circuit is configured to perform the second program control operation by applying the bit line voltage having a lower level than a second predetermined level to the bit lines in loops before pass-determination occurs as a result of a verification operation among the plurality of loops and by applying the bit line voltage having the second predetermined level to the bit lines in a loop in which the pass-determination occurs as the result of the verification operation and subsequent loops among the plurality of loops.