US 12,242,729 B2
Reconfigurable on-chip memory bank, reconfigurable on-chip memory, system-on-chip having same mounted thereon, and method for using reconfigurable on-chip memory
Wongyu Shin, Seongnam-si (KR); and Jinwook Oh, Seongnam-si (KR)
Assigned to Rebellions Inc., Seongnam-si (KR)
Filed by Rebellions Inc., Seongnam-si (KR)
Filed on Oct. 12, 2022, as Appl. No. 18/046,100.
Claims priority of application No. 10-2021-0161074 (KR), filed on Nov. 22, 2021.
Prior Publication US 2023/0161480 A1, May 25, 2023
Int. Cl. G06F 3/06 (2006.01); G06N 3/063 (2023.01); G06N 3/08 (2023.01)
CPC G06F 3/0613 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06N 3/063 (2013.01); G06N 3/08 (2013.01)] 31 Claims
OG exemplary drawing
 
24. A system-on-chip having a reconfigurable on-chip memory mounted thereon, comprising:
a plurality of processing units; and
an on-chip memory comprising a plurality of dedicated areas and a common area for the plurality of processing units, each of the plurality of dedicated areas associated with a respective one of the plurality of processing units,
wherein the on-chip memory comprises a memory bank comprising a memory cell array and a bank controller, the bank controller being configured to:
assign a calculation task to a processing unit;
obtain a path control signal according to the calculation task, wherein the path control signal indicates an interface to be used to transmit or receive data for the calculation task;
read or write the data for the calculation task from or onto the on-chip memory by using a first address system when the path control signal indicates using a first interface; and
read or write the data for the calculation task from or onto the on-chip memory by using a second address system different from the first address system when the path control signal indicates using a second interface;
wherein the size of at least one of the plurality of dedicated areas and the size of the common area change during runtime.