US 12,242,724 B2
Conversion of access data based on memory device size
Mow Yiak Goh, Boise, ID (US); and Mark Clouse, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 14, 2022, as Appl. No. 17/944,509.
Prior Publication US 2024/0086067 A1, Mar. 14, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0607 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0673 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory device comprising an array of memory cells;
a mode register coupled to the array;
an address decoder coupled to the array; and
a memory controller coupled to the memory device, the memory controller configured to cause performance of a memory access comprising:
receiving access data associated with a first memory device size to access data stored in the memory device, wherein the memory device is a second memory device size;
accessing address data in the mode register, wherein the address data in the mode register comprises mask data and force data; and
accessing the data in the memory device that is the second memory device size using the access data.