| CPC G06F 21/72 (2013.01) | 10 Claims |

|
1. A circuit, comprising:
a plurality of first logic gates implementing a first portion of a combinational circuit;
a memory device storing an encrypted look-up table portion comprising first information implementing gate logic of a plurality of second logic gates of a second portion of the combinational circuit, the first information being stored in an encrypted look-up table format and protecting the gate logic of the plurality of second logic gates from being determined from the plurality of first logic gates; and
a processor configured to (i) generate a decrypted look-up table portion comprising second information by decrypting at least a portion of the first information when the circuit is enabled, (ii) cause the plurality of first logic gates to use the second information to generate at least one output in accordance with operations of the combinational circuit, and (ii) remove the decrypted look-up table portion from the circuit upon detection of a trigger event;
wherein functions of the second portion of the combinational circuit are obfuscated when the circuit is in an at-rest state;
wherein the first information implementing the gate logic of the plurality of second logic gates is (i) only stored by the circuit in the encrypted look-up table format when the first information is not in use by the circuit, and (ii) at least partially stored by the circuit in the encrypted look-up table format and at least partially stored by the circuit in a decrypted look-up table format when the first information is in use by the circuit.
|