| CPC G06F 15/80 (2013.01) [G06F 9/30043 (2013.01); G06F 9/44505 (2013.01)] | 20 Claims | 

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               1. A multi-core processor comprising: 
            a primary processor core comprising a first instruction space and configured to: 
                execute a first code segment in a target program, wherein the target program further comprises a second code segment, wherein the first code segment is compatible with the first instruction space; and 
                  send an address of the second code segment; and 
                a secondary processor core coupled to the primary processor core, comprising a configuration interface and a second instruction space that is compatible with the second code segment, and configured to: 
              receive the address through the configuration interface; 
                  load the second code segment based on the address; and 
                  execute the second code segment. 
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