US 12,242,400 B2
Memory device interface communicating with set of data bursts corresponding to memory dies via dedicated portions for command processing
Luigi Pilolli, L'Aquila (IT)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Feb. 20, 2024, as Appl. No. 18/582,488.
Application 18/582,488 is a continuation of application No. 17/825,632, filed on May 26, 2022, granted, now 11,934,325.
Application 17/825,632 is a continuation of application No. 17/081,483, filed on Oct. 27, 2020, granted, now 11,347,663, issued on May 31, 2022.
Prior Publication US 2024/0248859 A1, Jul. 25, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/16 (2006.01); G06F 13/22 (2006.01); G06F 13/28 (2006.01); G06F 13/40 (2006.01)
CPC G06F 13/1668 (2013.01) [G06F 13/1615 (2013.01); G06F 13/22 (2013.01); G06F 13/28 (2013.01); G06F 13/4068 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
communicating, by a controller, a first access command to a first memory device via a command interface portion of a memory device interface;
communicating a second access command to second memory device via the command interface portion of the memory device interface;
causing communication of a data burst between the controller and the first memory device corresponding to the first access command via a data burst interface portion of the memory device interface; and
communicating a status polling communication via the memory device interface, wherein the status polling communication is communicated via the memory device interface concurrently with the data burst via the data burst interface portion of the memory device interface.