US 12,242,399 B2
Peripheral component handling of memory read requests
Jacob Joseph, Rotherham (GB); Tessil Thomas, Cambridge (GB); Arthur Brian Laughton, Hathersage (GB); Anitha Kona, Austin, TX (US); and Jamshed Jalal, Austin, TX (US)
Assigned to Arm Limited, Cambridge (GB)
Filed by Arm Limited, Cambridge (GB)
Filed on Feb. 23, 2022, as Appl. No. 17/678,174.
Prior Publication US 2023/0267081 A1, Aug. 24, 2023
Int. Cl. G06F 13/00 (2006.01); G06F 12/0862 (2016.01); G06F 12/0891 (2016.01); G06F 12/1045 (2016.01); G06F 13/16 (2006.01)
CPC G06F 13/1668 (2013.01) [G06F 12/0862 (2013.01); G06F 12/0891 (2013.01); G06F 12/1054 (2013.01); G06F 12/1063 (2013.01); G06F 13/161 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A data processing system comprising:
an interconnect comprising a system cache;
a peripheral component coupled to the interconnect; and
a memory coupled to the interconnect,
wherein the peripheral component comprises a request ordering queue configured to queue received memory access requests in a receipt order, and wherein the peripheral component is configured to issue the memory access requests to the interconnect in the receipt order,
wherein the peripheral component is configured to delay issuance of a memory read request of the memory access requests to the interconnect until a completion response for all memory write requests ahead of the memory read request in the memory access requests has been received from the interconnect,
wherein the peripheral component is responsive to receipt of the memory read request to issue a memory read prefetch request comprising a physical address to the interconnect,
and the interconnect is responsive to the memory read prefetch request to cause data associated with the physical address in the memory to be cached in the system cache.