US 12,242,396 B2
PC-based memory permissions
Jeffry E. Gonion, Campbell, CA (US); and Bernard J. Semeria, Palo Alto, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jun. 28, 2023, as Appl. No. 18/343,125.
Claims priority of provisional application 63/356,074, filed on Jun. 28, 2022.
Prior Publication US 2023/0418767 A1, Dec. 28, 2023
Int. Cl. G06F 12/14 (2006.01); G06F 9/30 (2018.01); G06F 12/1027 (2016.01); G06F 21/52 (2013.01)
CPC G06F 12/1483 (2013.01) [G06F 9/30076 (2013.01); G06F 9/30189 (2013.01); G06F 12/1027 (2013.01); G06F 12/1475 (2013.01); G06F 21/52 (2013.01); G06F 2221/034 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a processor that includes:
a permission table circuit configured to store a plurality of permissions for accesses to memory, wherein the permission table circuit is indexed by a particular permission table index corresponding to a particular instruction to provide a particular permission for a particular memory access by the particular instruction;
a secondary execution privileges table circuit configured to store a plurality of secondary execution privilege values, wherein the secondary execution privileges table circuit is indexed by a particular secondary execution privileges index corresponding to the particular instruction to provide a particular secondary execution privileges value for the particular instruction; and
a control circuit coupled to the permission table circuit and the secondary execution privileges table circuit configured to:
generate the particular permission table index and the particular secondary execution privileges index based on:
a first value corresponding to a first memory address indicated by the particular instruction; and
a second value corresponding to a second memory address indicative of a program counter value used to fetch the particular instruction; and
determine, based on permissions retrieved from the permission table circuit and the secondary execution privileges table circuit, access permissions for the particular memory access by the particular instruction.