US 12,242,390 B2
Data security for memory and computing systems
Brett K. Dodds, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 1, 2023, as Appl. No. 18/241,699.
Application 18/241,699 is a continuation of application No. 16/849,927, filed on Apr. 15, 2020, granted, now 11,748,271.
Prior Publication US 2024/0004802 A1, Jan. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/00 (2006.01); G06F 9/30 (2018.01); G06F 12/02 (2006.01); G06F 12/1009 (2016.01); G06F 12/14 (2006.01); G06F 21/79 (2013.01); G06F 21/10 (2013.01)
CPC G06F 12/1408 (2013.01) [G06F 9/30029 (2013.01); G06F 12/0246 (2013.01); G06F 12/1009 (2013.01); G06F 21/79 (2013.01); G06F 21/107 (2023.08); G06F 2212/7201 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a core configured to process data;
a security circuit communicatively coupled to the core and configured to provide one or more security functions,
wherein the one or more security functions are transparent to a developer of an application that is different from both an operating system and a privileged software,
wherein the one or more security functions are transparent such that the one or more security functions are implemented without corresponding adjustments on the application, the operating system, and the privileged software, and
wherein the security circuit includes:
a first portion configured to track a scrambling key associated with the data, and
a second portion configured to:
encrypt the data according to the scrambling key prior to the data being written to one or more memory cells, and
recover the data based on decrypting using the scrambling key, data read from the memory cells.