US 12,242,383 B2
Recording a memory value trace for use with a separate cache coherency protocol trace
Jordi Mola, Bellevue, WA (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Appl. No. 17/921,067
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
PCT Filed Apr. 30, 2021, PCT No. PCT/US2021/030220
§ 371(c)(1), (2) Date Oct. 24, 2022,
PCT Pub. No. WO2021/225895, PCT Pub. Date Nov. 11, 2021.
Claims priority of application No. 101767 (LU), filed on May 5, 2020.
Prior Publication US 2023/0350804 A1, Nov. 2, 2023
Int. Cl. G06F 12/0831 (2016.01); G06F 11/34 (2006.01); G06F 11/36 (2006.01); G06F 11/362 (2025.01); G06F 12/0891 (2016.01)
CPC G06F 12/0835 (2013.01) [G06F 11/3636 (2013.01); G06F 12/0891 (2013.01); G06F 11/3476 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A computer system comprising:
a processor comprising a plurality of processing units and a cache;
a memory; and
a computer-readable medium having stored thereon computer-executable instructions that are executable by the processor to cause the computer system to record a replayable execution trace based on recording cache coherency protocol (CCP) messages into a first trace, and on recording one or more memory snapshots into a second trace, the CCP messages being usable to obtain memory values from one or more memory snapshots,
the computer-executable instructions including instructions that are executable by the processor to cause the computer system to at least:
determine that tracing of execution, by the plurality processing units, of a first execution context is to be enabled;
based on determining that tracing of execution of the first execution context is to be enabled:
initiate logging, into the second trace, of one or more memory snapshots of a memory space of the first execution context; and
enable a hardware tracing feature of the processor, which causes the processor to log, into the first trace, one or more CCP messages generated in response to one or more memory access, by one or more of the plurality of processing units, into the memory space of the first execution context;
after enabling the hardware tracing feature of the processor, perform at least one of the following in connection with execution of a second execution context:
log, into one or more of the first trace or the second trace, a write by the second execution context into the memory space of the first execution context;
log, into the second trace, an identity of a file mapped by the second execution context into the memory space of the first execution context;
based at least on the second execution context writing to a cache line in the cache that overlaps with a memory location in memory space of the first execution context, evict, or mark as invalid, the cache line from the cache; or
based at least on the second execution context writing to a memory region within the memory space of the first execution context, mark the memory region as needing to be logged in connection with execution of the first execution context; and encrypt at least a portion of the second trace.