US 12,242,381 B2
In-memory zero value detection
Elad Sity, Kfar Saba (IL); and Eliad Hillel, Herzliya (IL)
Assigned to NeuroBlade Ltd., Tel Aviv (IL)
Filed by NeuroBlade Ltd., Tel Aviv (IL)
Filed on Feb. 11, 2022, as Appl. No. 17/669,657.
Application 17/669,657 is a continuation of application No. PCT/IB2020/000665, filed on Aug. 13, 2020.
Claims priority of provisional application 62/983,174, filed on Feb. 28, 2020.
Claims priority of provisional application 62/971,912, filed on Feb. 7, 2020.
Claims priority of provisional application 62/907,659, filed on Sep. 29, 2019.
Claims priority of provisional application 62/886,328, filed on Aug. 13, 2019.
Prior Publication US 2022/0164284 A1, May 26, 2022
Int. Cl. G06F 12/08 (2016.01); G06F 3/06 (2006.01); G06F 12/06 (2006.01); G06F 12/0802 (2016.01); G06F 12/14 (2006.01); G06F 13/16 (2006.01); G06F 15/78 (2006.01)
CPC G06F 12/0802 (2013.01) [G06F 3/0625 (2013.01); G06F 3/0637 (2013.01); G06F 3/0673 (2013.01); G06F 12/0646 (2013.01); G06F 12/1458 (2013.01); G06F 13/1657 (2013.01); G06F 13/1668 (2013.01); G06F 15/786 (2013.01); G06F 2212/1056 (2013.01); G06F 2212/60 (2013.01); G06F 2212/7202 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A memory unit comprising:
a memory array including a plurality of memory banks;
at least one controller configured to control at least one aspect of read operations relative to the plurality of memory banks;
at least one multi-bit zero value detection logic unit configured to detect a multi-bit zero value associated with data and prevent retrieval of the data, wherein the data is stored in a particular address of the plurality of memory banks;
at least one read-disable element configured to interrupt a read command associated with the particular address when the at least one multi-bit zero value detection logic unit detects the multi-bit zero value associated with the particular address; and
wherein the at least one controller is configured to return a multi-bit zero value indicator to one or more circuits in response to a multi-bit zero value detection by the at least one multi-bit zero value detection logic unit.