US 12,242,346 B2
Global column repair with local column decoder circuitry, and related apparatuses, methods, and computing systems
Christopher G. Wieduwilt, Boise, ID (US); and Fatma Arzum Simsek-Ege, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 4, 2022, as Appl. No. 17/937,924.
Prior Publication US 2024/0111628 A1, Apr. 4, 2024
Int. Cl. G06F 11/10 (2006.01); G11C 29/00 (2006.01)
CPC G06F 11/1092 (2013.01) [G11C 29/702 (2013.01); G11C 29/76 (2013.01); G11C 29/78 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory array including memory cells organized in column planes, the column planes associated with respective column addresses;
local column decoder circuitry including all two or more local column decoder circuits, each local column decoder circuit of the two or more local column decoder circuits local to an associated column plane of the column planes, the local column decoder circuitry configured to, if enabled, decode a received column address signal to generate a column select signal; and
global column repair circuitry coupled to each local column decoder circuit of the two or more local column decoder circuits, the global column repair circuitry comprising:
column address drivers corresponding to respective ones of the column planes, the column address drivers configured to, if enabled, drive the received column address signal to the local column decoder circuitry of respective ones of the column planes;
data storage elements configured to store known defective column addresses corresponding to defective column planes; and
match circuitry coupled to each local column decoder circuit of the two or more local column decoder circuits, the match circuitry configured to:
compare a received column address indicated by the received column address signal to the known defective column addresses; and
disable a column address driver corresponding to a defective column plane responsive to a determination that the received column address matches a known defective column address associated with the defective column plane.