US 12,242,344 B2
DRAM assist error correction mechanism for DDR SDRAM interface
Dimin Niu, Sunnyvale, CA (US); Mu-Tien Chang, San Jose, CA (US); Hongzhong Zheng, Los Gatos, CA (US); Hyun-Joong Kim, Hwaseong-si (KR); Won-hyung Song, Osan-si (KR); and Jangseok Choi, Campbell, CA (US)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 28, 2023, as Appl. No. 18/127,329.
Application 16/276,369 is a division of application No. 15/286,460, filed on Oct. 5, 2016, granted, now 10,268,541, issued on Apr. 23, 2019.
Application 18/127,329 is a continuation of application No. 17/319,844, filed on May 13, 2021, granted, now 11,625,296.
Application 17/319,844 is a continuation of application No. 16/276,369, filed on Feb. 14, 2019, granted, now 11,010,242, issued on May 18, 2021.
Claims priority of provisional application 62/375,381, filed on Aug. 15, 2016.
Prior Publication US 2023/0229555 A1, Jul. 20, 2023
Int. Cl. G06F 11/00 (2006.01); G06F 11/10 (2006.01); G11C 5/04 (2006.01); G11C 29/42 (2006.01); G11C 29/52 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/1048 (2013.01); G11C 5/04 (2013.01); G11C 29/42 (2013.01); G11C 29/52 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A memory error correction method for correcting a memory error of a volatile computer memory, the method comprising:
sending data from the volatile computer memory, which comprises a memory channel, to a device that is separate from the volatile computer memory; and
determining, with the volatile computer memory, a characteristic of a first memory error based on whether a number of memory errors of the data that match the first memory error meets a threshold.