US 12,242,343 B2
Command address fault detection using a parity pin
Melissa I. Uribe, El Dorado Hills, CA (US); Aaron P. Boehm, Boise, ID (US); Scott E. Schaefer, Boise, ID (US); and Steffen Buch, Taufkirchen (DE)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 25, 2022, as Appl. No. 18/049,454.
Prior Publication US 2024/0134744 A1, Apr. 25, 2024
Prior Publication US 2024/0232008 A9, Jul. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G06F 11/07 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/0772 (2013.01); G06F 11/102 (2013.01)] 25 Claims
OG exemplary drawing
 
20. A method performed by a memory device, comprising:
receiving, from a host device via a command address (CA) bus and during a unit interval of a plurality of unit intervals, a set of CA bits associated with a CA word;
receiving, from the host device via a parity bus and during the unit interval, a first parity bit that is based on the set of CA bits and a parity generation process;
generating a second parity bit based on the set of CA bits and the parity generation process; and
transmitting an alert signal to the host device, via a unidirectional alert bus, based on a result of comparing the first parity bit and the second parity bit, wherein the unidirectional alert bus is different than the CA bus.