US 12,242,341 B2
Error correction method, memory system and memory controller
Hua Tan, Wuhan (CN); Dili Wang, Wuhan (CN); Xuqing Jia, Wuhan (CN); and Teng Zhou, Wuhan (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Sep. 25, 2023, as Appl. No. 18/473,972.
Claims priority of application No. 202310804798.4 (CN), filed on Jun. 30, 2023.
Prior Publication US 2025/0004877 A1, Jan. 2, 2025
Int. Cl. G06F 11/10 (2006.01)
CPC G06F 11/1056 (2013.01) [G06F 11/1068 (2013.01); G06F 11/108 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An error correction method for a memory system, comprising:
obtaining a corresponding first soft data according to first hard read data and cached second hard read data after hard decision decoding for the first hard read data fails, wherein the first hard read data is read according to a first hard read voltage, and the second hard read data is read according to a second hard read voltage before reading the first hard read data; and
performing first soft decision decoding according to the first soft data and the first hard read data, or performing first soft decision decoding according to the first soft data and the second hard read data,
wherein the first hard read voltage is one of a plurality of re-read voltages with a certain offset from an initial read voltage, and the second hard read voltage is the initial read voltage or a re-read voltage of the plurality of re-read voltages except the first hard read voltage.