US 12,242,340 B2
Memory cell array unit
Lui Sakai, Kanagawa (JP); and Yasuo Kanda, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Tokyo (JP)
Appl. No. 18/248,541
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Oct. 7, 2021, PCT No. PCT/JP2021/037180
§ 371(c)(1), (2) Date Apr. 11, 2023,
PCT Pub. No. WO2022/085470, PCT Pub. Date Apr. 28, 2022.
Claims priority of application No. 2020-175666 (JP), filed on Oct. 19, 2020.
Prior Publication US 2023/0376376 A1, Nov. 23, 2023
Int. Cl. G06F 11/00 (2006.01); G06F 11/10 (2006.01); H10B 63/00 (2023.01)
CPC G06F 11/1044 (2013.01) [G06F 11/10 (2013.01); G06F 11/1028 (2013.01); H10B 63/00 (2023.02)] 7 Claims
OG exemplary drawing
 
1. A memory cell array unit comprising:
a memory cell array that includes a plurality of n-bit allocation memory cells, wherein
the memory cell array is configured to receive a control signal from a memory controller,
the control signal comprises n-bit data, and
the memory controller allocates the plurality of n-bit allocation memory cells to the n-bit data; and
a microcontroller configured to:
read and write the n-bit data from and into the memory cell array based on the control signal;
receive n-bit write data and control data from a host computer;
write n−1-bit write data into a plurality of n−1-bit allocation memory cells, wherein the n-bit write data includes n−1-bit write data;
determine a defect in the plurality of n-bit allocation memory cells based on the n-bit write data and the control data;
determine a defective allocation memory cell of the plurality of n-bit allocation memory cells based on the determined defect; and
exclude the defective allocation memory cell and first data, wherein
the n−1-bit write data includes the first data, and
the first data corresponds to a least significant bit of the n−1-bit write data.