| CPC G06F 1/08 (2013.01) [H03L 7/093 (2013.01)] | 20 Claims |
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1. A signal synthesizer circuit, comprising:
a clock source, a direct digital synthesizer (DDS) circuit, a first signal path, a second signal path, an output being connected to the first signal path and the second signal path, and a selection circuit,
wherein the first signal path is arranged in parallel to the second signal path,
wherein the clock source is configured to generate or receive a clock signal having a predefined frequency,
wherein the DDS circuit is configured to receive the clock signal and to generate a DDS signal based on the clock signal,
wherein the first signal path is connected to the DDS circuit so as to receive the DDS signal generated based on the clock signal, wherein the first signal path comprises a multiplier circuit being configured to multiply a frequency of the DDS signal by a multiplication factor, thereby obtaining a frequency-multiplied DDS signal,
wherein the second signal path is connected to the clock source so as to receive the clock signal, wherein the clock signal received by the second signal path is the same clock signal that is received by the DDS circuit, wherein the second signal path comprises a mixer circuit being connected to the clock source and to the multiplier circuit so as to receive the clock signal and the frequency-multiplied DDS signal,
wherein the mixer circuit is configured to mix the clock signal with the frequency-multiplied DDS signal, thereby obtaining a mixed DDS signal, wherein a frequency of the mixed DDS signal corresponds to the sum of frequencies of the clock signal received by the second signal path and of the frequency-multiplied DDS signal,
wherein the selection circuit is connected to both the first signal path and the second signal path, and
wherein the selection circuit is configured to selectively forward the mixed DDS signal and/or the frequency-multiplied DDS signal to the output.
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