US 12,242,202 B2
Method for overlay error correction
Shih-Yuan Ma, New Taipei (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Jan. 4, 2022, as Appl. No. 17/568,151.
Prior Publication US 2023/0213874 A1, Jul. 6, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G03F 7/00 (2006.01)
CPC G03F 7/70633 (2013.01) 19 Claims
 
1. A method for overlay error correction, comprising:
obtaining an overlay error based on a lower-layer pattern and an upper-layer pattern of a wafer, wherein the lower-layer pattern is obtained by first fabrication equipment through which the wafer passes, and the upper-layer pattern is obtained by exposure equipment;
generating a corrected overlay error based on the overlay error and fabrication processes perforated on the wafer after the first fabrication equipment and prior to the exposure equipment; and
adjusting the exposure equipment based on the corrected overlay error.