US 12,242,199 B2
Method of using wafer stage
Yung-Yao Lee, Hsinchu (TW); Wei Chih Lin, Hsinchu (TW); and Chih Chien Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Aug. 10, 2023, as Appl. No. 18/448,110.
Application 18/448,110 is a division of application No. 17/832,297, filed on Jun. 3, 2022.
Application 17/832,297 is a division of application No. 17/083,868, filed on Oct. 29, 2020, granted, now 11,378,889, issued on Jul. 5, 2022.
Prior Publication US 2023/0400775 A1, Dec. 14, 2023
Int. Cl. H01L 21/027 (2006.01); G03F 7/00 (2006.01)
CPC G03F 7/70341 (2013.01) [G03F 7/70725 (2013.01); H01L 21/0274 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of controlling a wafer stage, the method comprising:
moving the wafer stage to position an immersion hood over a first sensor in the wafer stage;
moving the wafer stage to position the immersion hood over a second sensor in the wafer stage;
moving the wafer stage to position the immersion hood over a first particle capture area on the wafer stage after moving the wafer stage to position the immersion hood over the second sensor;
moving the wafer stage to define a routing track over the first particle capture area; and
moving the wafer stage to position the immersion hood over an area for receiving a wafer on the wafer stage after defining the routing track over the first particle capture area.