| CPC G03F 1/70 (2013.01) [G03F 1/36 (2013.01); G03F 1/44 (2013.01); G06F 16/51 (2019.01); G06F 30/392 (2020.01); G06F 2111/20 (2020.01)] | 20 Claims | 

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               1. A method to perform mask synthesis for a circuit design, the method comprising: 
            receiving the circuit design representing a physical layout of a circuit, the circuit design comprising geometric shapes; 
                identifying a region within the circuit design; 
                identifying a plurality of mask patterns for the region, wherein at least some of the plurality of mask patterns are overlapping, each mask pattern using a vector representation of geometric shapes; 
                generating a plurality of image mask representations comprising, for each mask pattern from the plurality of mask patterns, rasterizing the mask pattern to generate an image mask representation comprising a plurality of pixel values; 
                determining a weighted aggregate of the plurality of image mask representations to generate an aggregate image mask representation, wherein a pixel value closer to center of the region is weighted higher than a pixel value far from the center of the region; and 
                generating, by a processing device, an aggregate mask pattern from the aggregate image mask representation. 
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