| CPC G02F 1/1368 (2013.01) [G02F 1/136286 (2013.01); H01L 27/1244 (2013.01); G02F 1/136213 (2013.01); H01L 27/1255 (2013.01)] | 16 Claims |
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1. An array substrate, comprising:
a gate of a thin film transistor, extending in a first direction;
a first electrode of the thin film transistor, comprising a first body and a first end that are connected to each other; and
a second electrode of the thin film transistor, comprising a second body and a second end that are connected to each other;
wherein an orthographic projection of the first body on a base of the array substrate and an orthographic projection of the second body on the base are located in an orthographic projection of the gate on the base, an orthographic projection of at least partial area of the first end on the base and an orthographic projection of at least partial area of the second end on the base do not overlap with the orthographic projection of the gate on the base, and an orthographic projection of the first end on the base and an orthographic projection of the second end on the base are both located on a same side of the orthographic projection of the gate on the base;
wherein in the first direction, an average distance from the first end to the second end is greater than an average distance from the first body to the second body;
wherein the first electrode further comprises a third end, and the first end and the third end are connected via the first body; the second electrode further comprises a fourth end, and the second end and the fourth end are connected via the second body; an orthographic projection of at least partial area of the third end on the base and an orthographic projection of at least partial area of the fourth end on the base do not overlap with the orthographic projection of the gate on the base; in the first direction, an average distance from the third end to the fourth end is greater than the average distance from the first body to the second body;
wherein the array substrate further comprises a gate line, a data line, a pixel electrode, a first trace and a second trace, wherein the data line intersects with the gate line and is insulated from the gate line, the gate is electrically connected to the gate line, the pixel electrode is located at a position defined by two adjacent data lines and two adjacent gate lines, the third end of the first electrode is electrically connected to the data line via the first trace, and the second end of the second electrode is electrically connected to the pixel electrode via the second trace;
wherein in a direction pointing from a junction between the first body and the third end to a junction between the first trace and the third end, a minimum distance from the third end to the data line is gradually reduced; and
in a direction pointing from a junction between the second body and the second end to a junction between the second trace and the second end, a minimum distance from the second end to the data line is gradually increased;
wherein the gate line comprises a first line segment and a second line segment, the first line segment intersects with and is insulated from the data line, and a partial area of the second line segment is used as the gate;
wherein a size of an orthographic projection of the second line segment on the base in a direction perpendicular to the first direction is greater than a size of an orthographic projection of the first line segment on the base in the direction perpendicular to the first direction.
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