US 12,242,122 B2
Multicomponent photonically intra-die bridged assembly
Philip Winterbottom, San Jose, CA (US); David Lazovsky, Los Gatos, CA (US); Ankur Aggarwal, Pleasanton, CA (US); Martinus Bos, San Jose, CA (US); and Subal Sahni, La Jolla, CA (US)
Assigned to Celestial AI Inc., Santa Clara, CA (US)
Filed by Celestial AI Inc., Santa Clara, CA (US)
Filed on Apr. 11, 2024, as Appl. No. 18/632,658.
Application 18/632,658 is a division of application No. 18/243,474, filed on Sep. 7, 2023, granted, now 12,124,095.
Application 18/243,474 is a continuation of application No. 18/123,083, filed on Mar. 17, 2023, granted, now 11,835,777, issued on Dec. 5, 2023.
Claims priority of provisional application 63/321,453, filed on Mar. 18, 2022.
Claims priority of provisional application 63/420,330, filed on Oct. 28, 2022.
Claims priority of provisional application 63/448,585, filed on Feb. 27, 2023.
Prior Publication US 2024/0272393 A1, Aug. 15, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G02B 6/42 (2006.01); G02B 6/43 (2006.01); G02F 1/015 (2006.01)
CPC G02B 6/4295 (2013.01) [G02B 6/4246 (2013.01); G02B 6/428 (2013.01); G02B 6/43 (2013.01); G02F 1/0157 (2021.01); G02B 6/4245 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A package comprising:
a first die comprising a first compute element and/or a first memory element, and a first region;
a second die comprising a second compute element and/or a second memory element, and a second region; and
a first bridging element bridging the first die and the second die;
wherein the first bridging element comprises:
a first interconnect region and a second interconnect region for electrical coupling to the first die and to the second die;
a first photonic path from the first interconnect region to the second interconnect region; and
a second photonic path from the second interconnect region to the first interconnect region;
and wherein:
a first portion (MOD1, PD1) of a photonic transceiver resides in a photonic integrated circuit (PIC) and is coupled between the first interconnect region on one side and the first photonic path and the second photonic path on another side, and wherein a second portion of the photonic transceiver resides in an electric integrated circuit (EIC), the first and the second portions being coupled via an electrical interconnect less than two millimeters (2 mm) in length.