US 12,241,933 B2
Integrated circuit margin measurement for structural testing
Evelyn Landman, Haifa (IL); Eyal Fayneh, Givatayim (IL); Shai Cohen, Haifa (IL); and Alex Khazin, Nesher (IL)
Assigned to PROTEANTECS LTD., Haifa (IL)
Appl. No. 18/014,642
Filed by PROTEANTECS LTD., Haifa (IL)
PCT Filed Jul. 5, 2021, PCT No. PCT/IL2021/050826
§ 371(c)(1), (2) Date Jan. 5, 2023,
PCT Pub. No. WO2022/009199, PCT Pub. Date Jan. 13, 2022.
Claims priority of provisional application 63/048,265, filed on Jul. 6, 2020.
Prior Publication US 2023/0258719 A1, Aug. 17, 2023
Int. Cl. G01R 31/3185 (2006.01); G01R 31/30 (2006.01); H03K 5/13 (2014.01)
CPC G01R 31/318594 (2013.01) [G01R 31/3016 (2013.01); G01R 31/318536 (2013.01); H03K 5/13 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for testing a semiconductor integrated circuit (IC), the method comprising:
scanning test patterns into internal circuits of the semiconductor IC, the internal circuits of the semiconductor IC comprising a margin measurement sensor;
measuring a margin, using the margin measurement sensor, the margin being measured based on a characteristic of a comparison between a test signal path of the semiconductor IC and a delayed signal path, the delayed signal path being a signal of the test signal path delayed by an adjustable delay time,
wherein the adjustable delay time is introduced by having each of the test patterns cause an incremental adjustment of the delay time; and
scanning out an output of the margin measurement sensor.