US 12,241,931 B1
Method and apparatus for capture clock control to minimize toggling during testing
Balaji Upputuri, Prakasam (IN); and Scott Mack, Rochester, MN (US)
Assigned to Marvell Asia Pte Ltd, Singapore (SG)
Filed by Marvell Asia Pte Ltd, Singapore (SG)
Filed on Jan. 11, 2023, as Appl. No. 18/153,269.
Claims priority of provisional application 63/299,001, filed on Jan. 12, 2022.
Int. Cl. G06F 11/10 (2006.01); G01R 31/317 (2006.01); G06F 11/07 (2006.01); G06F 11/30 (2006.01); G06F 13/16 (2006.01); G06F 13/28 (2006.01)
CPC G01R 31/31727 (2013.01) [G01R 31/31703 (2013.01); G01R 31/31725 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of testing an integrated circuit device, the method comprising:
detecting a number of integrated clock gates in the integrated circuit device, each integrated clock gate being disposed in a respective branch of a clock tree of the integrated circuit device to stop clock propagation in the respective branch of the clock tree;
for each detected integrated clock gate, comparing an integrated clock gate fanout with a threshold number of registers, the integrated clock gate fanout being a number of digital inputs that the output of each integrated clock gate can feed;
determining, when the integrated clock gate fanout is greater than the threshold number of registers, whether a function-enable path of an existing integrated clock gate is timing-critical; and
when it is determined that the function-enable path of the existing integrated clock gate is timing-critical, inserting, into the integrated circuit device, an additional integrated clock gate and a test point, as a clock input to the existing integrated clock gate.