US 12,241,912 B2
Socketless or flush mount QFN (quad flat no lead) test board, fixture, and method
David Yu Shan Sun, Rancho Palos Verdes, CA (US); and Alfredo Rene Lara, Norwalk, CA (US)
Assigned to RAYTHEON COMPANY, Waltham, MA (US)
Filed by Raytheon Company, Waltham, MA (US)
Filed on Oct. 21, 2022, as Appl. No. 18/048,558.
Claims priority of provisional application 63/270,841, filed on Oct. 22, 2021.
Prior Publication US 2023/0137253 A1, May 4, 2023
Int. Cl. G01R 1/04 (2006.01); G01R 31/28 (2006.01)
CPC G01R 1/0408 (2013.01) [G01R 31/2891 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A method of testing an integrated circuit with testing apparatus, the method comprising:
providing a test fixture comprising a toggle member configured for movement along a first axis;
fixedly coupling a plurality of pogo pins to the toggle member in a predetermined orientation, wherein the plurality of pogo pins are configured for movement along the first axis when the toggle member is moved, wherein each respective pogo pin includes a respective plunger, from a plurality of plungers, the respective plunger configured to move within the pogo pin along the first axis;
providing a test board in operable communication with the toggle member, the test board configured to have a first region for receiving a device under test (DUT), the test board having formed thereon, within the first region, at least one conductive region configured to substantially align with a corresponding conductor disposed on an outer surface of a device under test;
configuring an arrangement of the plurality of pogo pins and respective plungers to make contact with a top surface of the DUT when the DUT is positioned to be aligned to and disposed on the first region of the test board; and
configuring the testing apparatus so that movement of the toggle member along a first axis translates to at least a portion of the plurality of plungers applying a pressure sufficient to the top surface of the DUT to ensure a flushmount electrical contact between the corresponding conductor of the DUT and the conductive region of the test board;
providing an integrated circuit (IC), the IC having a first surface with a plurality of conductors disposed thereon, wherein the first surface has a first coplanarity;
performing a hot solder dip (HSD) process on the IC to coat the plurality of conductors with a first thickness of solder coating, to create a dipped IC;
burnishing the first thickness of solder coating to a second coplanarity, wherein the second coplanarity is more planar than the first coplanarity, to create a dipped burnished IC; and
configuring the dipped burnished IC as the DUT within the test fixture.