US 12,241,857 B2
High density and multiplexed nanopore devices with transverse tunneling junction for biomolecule detection and sequencing
Quan Qing, Chandler, AZ (US)
Assigned to Arizona Board of Regents on Behalf of Arizona State University, Scottsdale, AZ (US)
Appl. No. 18/550,881
Filed by ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY, Scottsdale, AZ (US)
PCT Filed Mar. 15, 2022, PCT No. PCT/US2022/020441
§ 371(c)(1), (2) Date Sep. 15, 2023,
PCT Pub. No. WO2022/197741, PCT Pub. Date Sep. 22, 2022.
Claims priority of provisional application 63/161,681, filed on Mar. 16, 2021.
Prior Publication US 2024/0151682 A1, May 9, 2024
Int. Cl. G01N 27/327 (2006.01); B01L 3/00 (2006.01)
CPC G01N 27/3278 (2013.01) [B01L 3/502707 (2013.01); B01L 2300/0645 (2013.01); B01L 2300/0896 (2013.01); B01L 2400/0415 (2013.01)] 27 Claims
OG exemplary drawing
 
1. A chip for measuring electrical and/or optical properties from one or more molecules, comprising:
a plurality of electronic devices, each of the plurality of electronic devices comprising:
a top fluidic channel/chamber and a bottom fluidic channel/chamber fabricated in a planar substrate, the top fluidic channel/chamber being sealed at a bottom of the electronic device and including a first open window at a top of the electronic device, and the bottom fluidic channel/chamber being sealed at the top of the electronic device and including a second open window at the bottom of the electronic device,
a first electrode and a second electrode positioned in a space of the electronic device between the top fluidic channel/chamber and the bottom fluidic channel/chamber, and
a nanogap having dimensions defined in part by a distance between the first electrode and the second electrode, the nanogap having a single path for a molecule to travel from the top fluidic channel/chamber to the bottom fluidic channel/chamber and/or from the bottom fluidic channel/chamber to the top fluidic channel/chamber,
wherein the distance is between about 1-100 nm, and wherein the nanogap has a narrowest bottleneck in the single path between the top fluidic channel/chamber and the bottom fluidic channel,
wherein the plurality of electronic devices are divided into a set number of different groups, and
wherein the chip further comprises one or more multiwell structures coupled to the chip, with individual wells of the one or more multiwell structures corresponding to each of the set number of different groups.