| CPC B41J 2/17546 (2013.01) [B41J 2/17513 (2013.01); B41J 2/17523 (2013.01); B41J 2/17543 (2013.01)] | 20 Claims |

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1. A printing system comprising:
a printing apparatus; and
a liquid accommodation container that is configured to be mounted in an accommodation section of the printing apparatus, wherein
the printing apparatus includes
a printing head, and
the accommodation section, the accommodation section including: (i) a liquid introduction portion that introduces a liquid to the printing head, and (ii) a plurality of apparatus-side terminals,
the liquid accommodation container includes
a liquid accommodation body configured to accommodate a liquid,
a liquid supply portion that is mounted at the liquid introduction portion of the printing apparatus and includes a liquid supply port for supplying a liquid to the liquid introduction portion from the liquid accommodation body,
a device configured with a processor, and
a plurality of terminals that are electrically coupled to the device,
the plurality of terminals include a data terminal and other terminals including a clock terminal, and
the printing system is configured to satisfy I, II, III, and IV as follows,
I: the processor is programmed to output to the data terminal provided in the plurality of terminals, a first response signal containing a first low voltage and outputs a second response signal containing a second high voltage and a second low voltage lower than the second high voltage,
II: the first response signal and the second response signal are output at a predetermined timing such that, in relation to a clock signal, the first response signal and the second response signal indicate to the printing apparatus that the data terminal does not have a short circuit with the other terminals other than the data terminal among the plurality of terminals and that the liquid accommodation container is being mounted in the printing apparatus,
III: the processor is programmed to output to the data terminal the first response signal followed by the second response signal, and
IV: the processor is configured to receive at the clock terminal provided in the other terminals, the clock signal in which a low voltage and a high voltage alternately repeat with a predetermined cycle,
the first low voltage is output to the data terminal at a first time in a cycle in which a voltage received at the clock terminal is the high voltage,
after the first low voltage is output, the second high voltage is output to the data terminal at a second time in a cycle in which the voltage received at the clock terminal is the low voltage, and
after the second high voltage is output, the second low voltage is output to the data terminal at a third time in a cycle in which the voltage received at the clock terminal is the high voltage.
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