US 12,240,245 B2
Logic circuitry
James Michael Gardner, Corvallis, OR (US); Scott A. Linn, Corvallis, OR (US); Stephen D. Panshin, Corvallis, OR (US); Jefferson P. Ward, Vancouver, WA (US); and David Owen Roethig, Vancouver, WA (US)
Assigned to Hewlett-Packard Development Company, L.P., Spring, TX (US)
Appl. No. 16/977,675
Filed by Hewlett-Packard Development Company, L.P., Spring, TX (US)
PCT Filed Dec. 3, 2018, PCT No. PCT/US2018/063643
§ 371(c)(1), (2) Date Sep. 2, 2020,
PCT Pub. No. WO2020/117198, PCT Pub. Date Jun. 11, 2020.
Prior Publication US 2021/0001635 A1, Jan. 7, 2021
Int. Cl. G06F 21/44 (2013.01); B41J 2/175 (2006.01); G06F 21/74 (2013.01); G06F 21/85 (2013.01)
CPC B41J 2/17526 (2013.01) [B41J 2/17566 (2013.01); G06F 21/44 (2013.01); G06F 21/74 (2013.01); G06F 21/85 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A logic circuit comprising:
a communications interface including a data contact to communicate via a communications bus;
an enablement contact, separate from the communication interface, to receive an input to enable the logic circuit; and
at least one memory register, comprising at least one reconfigurable address register,
wherein the logic circuit is configured, such that, when enabled, it responds to communications sent via the communication bus, based at least in part on a reconfigured address transmitted to the logic circuit, the reconfigured address held in the at least one reconfigurable address register, wherein the reconfigured address is a bus address associated with the logic circuit, and
wherein the reconfigured address is reconfigurable between a first address and a second address, the first address associated with at least one first function or first data that is different from at least one second function or second data associated with the second address.