US RE49,854 E1
Systems and methods for minimizing static leakage of an integrated circuit
Randy J. Caplan, Hoschton, GA (US); and Steven J. Schwake, San Jose, CA (US)
Assigned to Mosaid Technologies Incorporated
Filed by Mosaid Technologies Incorporated, Ottawa (CA)
Filed on Dec. 23, 2020, as Appl. No. 17/131,912.
Application 12/620,749 is a division of application No. 11/998,762, filed on Nov. 30, 2007, granted, now 7,642,836, issued on Jan. 5, 2010.
Application 11/998,762 is a division of application No. 11/900,971, filed on Sep. 14, 2007, granted, now 7,382,178, issued on Jun. 3, 2008.
Application 13/158,862 is a continuation of application No. 14/209,455, filed on Mar. 13, 2014, granted, now RE48410.
Application 13/158,862 is a continuation of application No. 12/620,749, filed on Nov. 18, 2009, granted, now 7,982,532, issued on Jul. 19, 2011.
Application 11/900,971 is a continuation in part of application No. 10/996,739, filed on Nov. 24, 2004, granted, now 7,279,956, issued on Oct. 9, 2007.
Application 17/131,912 is a reissue of application No. 13/158,862, filed on Jun. 13, 2011, granted, now 8,134,406, issued on Mar. 13, 2012.
Application 14/209,455 is a reissue of application No. 13/158,862, filed on Jun. 13, 2011, granted, now 8,134,406, issued on Mar. 13, 2012.
Claims priority of provisional application 60/586,565, filed on Jul. 9, 2004.
Int. Cl. G05F 1/10 (2006.01); H03K 19/00 (2006.01)
CPC H03K 19/0013 (2013.01) [H03K 19/0016 (2013.01)] 10 Claims
OG exemplary drawing
 
[ 24. An integrated circuit comprising:
two power supply terminals configured to power the integrated circuit, said power supply terminals including a Vdd positive supply terminal and a Vss ground terminal together defining a range of logic levels;
a logic component, the logic component being either a logic gate or a storage cell;
a sleep transistor in series with the logic component and an electrical connection to one of said power supply terminals;
a voltage generator configured to selectively generate a voltage outside said range of logic levels for application to said sleep transistor during a power down mode, and another voltage outside the range of logic levels for application to said sleep transistor when in a mode other than said power down mode, responsive to an enable signal; and
a control circuit configured to control said voltage generator to adequately minimize leakage current through said sleep transistor during said power down mode, comprising:
a first voltage divider configured to provide a voltage reference;
a second voltage divider configured to provide a variable voltage reference responsive to said voltage outside said range of logic levels; and
a comparator having a first input coupled to receive the voltage reference from the first voltage divider, a second input coupled to receive the variable voltage reference from the second voltage divider, and an output coupled to provide the enable signal to the voltage generator. ]