US 11,917,833 B2
Thin film transistor deck selection in a memory device
Daniele Vimercati, El Dorado Hills, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 18, 2022, as Appl. No. 17/968,593.
Application 17/968,593 is a continuation of application No. 17/327,004, filed on May 21, 2021, granted, now 11,502,091.
Prior Publication US 2023/0112259 A1, Apr. 13, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/22 (2006.01); H10B 53/30 (2023.01); H10B 53/20 (2023.01); H10B 53/40 (2023.01)
CPC H10B 53/30 (2023.02) [G11C 11/221 (2013.01); G11C 11/2255 (2013.01); G11C 11/2259 (2013.01); G11C 11/2273 (2013.01); H10B 53/20 (2023.02); H10B 53/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a plurality of sets of memory cells, each set of memory cells associated with a respective level above a substrate;
a plurality of access line decoders, each access line decoder operable to couple with a respective subset of the plurality of sets of memory cells; and
a plurality of sets of access lines, each set of access lines coupled with a respective set of memory cells of the plurality of sets of memory cells and operable to couple with an access line decoder of the plurality of access line decoders via a respective set of transistors above the substrate.