CPC H10B 41/27 (2023.02) [G11C 5/025 (2013.01); G11C 5/06 (2013.01); H01L 21/768 (2013.01); H10B 43/27 (2023.02)] | 16 Claims |
1. A microelectronic device, comprising:
a stack structure comprising a vertically alternating sequence of conductive material and insulative material arranged in tiers, the stack structure having blocks separated from one another by first dielectric slot structures, each of the blocks comprising:
two crest regions;
an uppermost stadium structure interposed between the two crest regions in a first horizontal direction and comprising opposing staircase structures each having steps comprising edges of an upper group of the tiers of the stack structure;
two bridge regions neighboring opposing sides of the uppermost stadium structure in a second horizontal direction orthogonal to the first horizontal direction and having upper surfaces substantially coplanar with upper surfaces of the two crest regions; and
at least one second dielectric slot structure partially within horizontal boundaries of the uppermost stadium structure in the first horizontal direction and horizontally overlapping the two bridge regions in the second horizontal direction,
the at least one second dielectric slot structure partially vertically extending through and partially segmenting each of the two bridge regions,
lowermost boundaries of the at least one second dielectric slot structure vertically overlying lowermost boundaries of the uppermost stadium structure such that upper portions of the two bridge regions are respectively partially non-continuous in the first horizontal direction while lower portions of the two bridge regions are respectively substantially continuous in first horizontal direction.
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