US 11,917,814 B2
Semiconductor device
Mitsunari Sukekawa, Hiroshima (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Apr. 1, 2022, as Appl. No. 17/711,972.
Prior Publication US 2023/0320072 A1, Oct. 5, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/315 (2023.02) [H10B 12/50 (2023.02)] 18 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory mat including a plurality of vertical memory cell transistors;
a shield structure surrounding each of the plurality of vertical memory cell transistors, the shield structure comprising a conductive material; and
a ring-shaped wiring above the shield structure, the ring-shaped wiring being connected to the shield structure in an edge region of the shield structure.