US 11,917,809 B2
Thin film transistor deck selection in a memory device
Daniele Vimercati, El Dorado Hills, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 13, 2022, as Appl. No. 17/863,970.
Application 17/863,970 is a continuation of application No. 17/327,035, filed on May 21, 2021, granted, now 11,393,822.
Prior Publication US 2023/0005916 A1, Jan. 5, 2023
Int. Cl. G11C 7/10 (2006.01); H10B 12/00 (2023.01); H01L 27/06 (2006.01); G11C 11/408 (2006.01); G11C 11/22 (2006.01); H01L 29/786 (2006.01); H10B 53/20 (2023.01)
CPC H10B 12/30 (2023.02) [G11C 11/221 (2013.01); G11C 11/2253 (2013.01); G11C 11/408 (2013.01); H01L 27/0688 (2013.01); H01L 29/78642 (2013.01); H10B 53/20 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a set of first memory cells of a memory die, the set of first memory cells associated with a first level above a substrate of the memory die;
a set of second memory cells of the memory die, the set of second memory cells associated with the first level;
a set of third memory cells of the memory die, the set of third memory cells associated with a second level above the substrate of the memory die;
a set of fourth memory cells of the memory die, the set of fourth memory cells associated with the second level;
a plurality of first access lines, each first access line of the plurality of first access lines coupled with a respective subset of the set of first memory cells and operable to couple with circuitry of a third level via a respective first transistor of a plurality of first transistors of the first level;
a plurality of second access lines, each second access line of the plurality of second access lines coupled with a respective subset of the set of second memory cells and operable to couple with the circuitry of the third level via a respective second transistor of a plurality of second transistors of the first level;
a plurality of third access lines, each third access line of the plurality of third access lines coupled with a respective subset of the set of third memory cells and operable to couple with the circuitry of the third level via a respective third transistor of a plurality of third transistors of the second level; and
a plurality of fourth access lines, each fourth access line of the plurality of fourth access lines coupled with a respective subset of the set of fourth memory cells and operable to couple with the circuitry of the third level via a respective fourth transistor of a plurality of fourth transistors of the second level.