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1. An apparatus comprising: a semiconductor substrate; an access transistor including channel, source and drain regions arranged in a vertical direction to the semiconductor substrate and a gate-electrode facing to the channel region; a storage capacitor coupled to one of the source and drain regions; a plurality of bit-lines including a bit-line coupled to the other of the source and drain regions; an air gap between adjacent two of the plurality of bit-lines, the air gap and the plurality of bit-lines in a same insulating layer; and a pull-out-electrode connected to the bit-line, wherein surfaces of the source and drain regions and the pull-out-electrode on the bit-line side is arranged at substantially the same height from the upper surface of the semiconductor substrate.
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